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NXP Semiconductors
PCA85132
LCD driver for low multiplex rates
The display RAM bitmap, Figure 12 , shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 159 which correspond with the
segment outputs S0 to S159. In multiplexed LCD applications the segment data of the
first, second, third, and fourth row of the display RAM are time-multiplexed with BP0,
BP1, BP2, and BP3 respectively.
columns
display RAM addresses/segment outputs (S)
rows
0
1
2
3
4
155 156 157 158 159
0
display RAM rows/
backplane outputs 1
(BP)
2
3
013aaa220
The display RAM bitmap shows the direct relationship between the display RAM addresses and
the segment outputs; and between the bits in a RAM word and the backplane outputs.
Fig 12. Display RAM bitmap
When display data is transmitted to the PCA85132, the received display bytes are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and does not wait for the acknowledge cycle as with the commands. Depending
on the current multiplex drive mode, data is stored singularly, in pairs, triples, or
quadruples. To illustrate the filling order, an example of a 7-segment numeric display
showing all drive modes is given in Figure 13 . The RAM filling organization depicted
applies equally to other LCD types.
The following applies to Figure 13 :
? In static drive mode the eight transmitted data bits are placed in row 0 as 1 byte.
? In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as 2 successive 4-bit RAM words.
? In 1:3 multiplex drive mode the 8 bits are placed in triples into row 0, 1, and 2 as 3
successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is not
recommended to use this bit in a display because of the difficult addressing. This last
bit may, if necessary, be controlled by an additional transfer to this address but care
should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 7.5.3 on page 25 ).
? In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as 2 successive 4-bit RAM words.
PCA85132
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 11 July 2013
? NXP B.V. 2013. All rights reserved.
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